
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity latch_32b is
	PORT (
	clk : in STD_LOGIC;
	latch_in : in STD_LOGIC_VECTOR(31 downto 0);
	latch_out : out STD_LOGIC_VECTOR(31 downto 0)
	);
end latch_32b;

architecture Behavioral of latch_32b is

begin
	process(clk)
		variable storage : STD_LOGIC_VECTOR(31 downto 0);
	begin
		if (clk'event and clk='1') then
			storage := latch_in;
			latch_out <= storage;
		end if;
	
	end process;


end Behavioral;

